ASIC Performance and Power Architect, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 3 years of experience in ASIC performance or power modeling, management, optimizations, and post-silicon characterization.
• Experience with SoC architecture and use case datapath with performance and power management concepts.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with performance in memory system and multimedia IPs in mobile SoCs (e.g., ISP, codecs, display processor).
• Experience in programming (e.g., Python) and database analysis (e.g., SQL).
• Experience in software power optimizations (e.g., Android, Linux) and post-silicon power productization.
• Knowledge of software and architectural design decisions on system power and thermal behavior.

About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Create use case workload and data flow models for Day of Use (DoU) power evaluation.
• Drive power and performance optimizations through SoC generations.
• Perform post-silicon profiling for power and performance model correlation.
• Collaborate with architecture team on power-performance trade-off analysis for engineering reviews and product roadmap decisions.